Seminars and Projects

Silicon Photonics

2007-08-23T08:58:00.000-07:00

Unlike electronicdata, optical signals can travel tens of kilometers without distortion or attenuation. One can also pack dozens of channels of high-speed data onto a single fiber,. Today, 40 separate signals, each running at 10 gigabits per second, can be squeezed onto a hair-thin fiber. Inside the PC, though, it’s copper all the way. Why? Because photonic components are expensive. Today’s devices are specialized components made from indium phosphide, lithium niobate, and other exotic materials that can’t be integrated onto silicon chips. That makes their assembly much more complex than the assembly of ordinary electronics, because the paths that the light travels must be painstakingly aligned to micrometer precision. In a sense, the photonics industry is where the electronics industry was a half century ago, before the breakthrough of the integrated circuit.

The only way for photonics to move into the mass market is to introduce integration, high-volume manufacturing, and low-cost assembly that is, to "siliconize" photonics. By that we mean integrating several different optical devices onto one silicon chip, rather than separately assembling each from exotic materials.

To understand how optical data might one day travel through silicon in our computers, it is needed to know how it travels over optical fiber today. First, a computer sends regular electrical data to an optical transmitter, where the signal is converted into pulses of light. The transmitter contains a laser and an electrical driver, which uses the source data to modulate the laser beam. Imprinted with the data, the beam travels through the glass fiber, encountering switches at various junctures that route the data to different destinations. At the destination, a photodetector reads and converts the data encoded in the photons back into electrical data.

Similar techniques could someday allow us to collapse the dozens of copper conductors that currently carry data between processors and memory chips into a single photonic link. To do that cheaply, though, we need to figure out how to render the optical components i.e the laser, the modulator, the photodetector, with the help of silicon

Silicon Photonics

Mirror http://snipurl.com/sphoton

Contributed By Richa

Clockless Chips -Asynchronous Processors

2007-08-23T08:44:00.000-07:00

**Clockless chips, Asynchronous ARM**

How fast is your personal computer?

When people ask this question, they are typically referring to the frequency of a minuscule clock inside the computer, a crystal oscillator that sets the basic rhythm used throughout the machine. In a computer with a speed of one gigahertz, for example, the crystal "ticks" a billion times a second. Every action of the computer takes place in tiny steps, each a billionth of a second long. A simple transfer of data may take only one step; complex calculations may take many steps. All operations, however, must begin and end according to the clock’s timing signals.

The use of a central clock also creates problems. As speeds have increased, distributing the timing signals has become more and more difficult. Present-day transistors can process data so quickly that they can accomplish several steps in the time that it takes a wire to carry a signal from one side of the chip to the other. Keeping the rhythm identical in all parts of a large chip requires careful design and a great deal of electrical power. Wouldn’t it be nice to have an alternative?

Clockless approach, which uses a technique known as asynchronous logic, differs from conventional computer circuit design in that the switching on and off of digital circuits is controlled individually by specific pieces of data rather than by a tyrannical clock that forces all of the millions of the circuits on a chip to march in unison. It overcomes all the disadvantages of a clocked circuit such as slow speed, high power consumption, high electromagnetic noise etc.

For these reasons the clockless technology is considered as the technology which is going to drive majority of electronic chips in the coming years.

http://snipurl.com/clockless

Contributed By: Mohsin

Network on chip(Seminar)

2007-08-21T06:31:00.000-07:00

Network-on-Chip (NoCs) represent a promising solution to complex on-chip communication problems. With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary. In this report, a new architecture template, called Network on chip (NoC) is developed for future integrated telecommunication systems.

The network-on-chip (NoC) design paradigm is seen as a way of enabling the integration of an exceedingly high number of computational and storage blocks in a single chip. which provides vertical integration of physical and architectural levels in system design. A chip consists of contiguous areas called regions, which are physically isolated from each other but have special mechanism for communication among each other. A region of NoC will be composed of computing resources in the form of processor cores and field programmable logic blocks, distributed storage resources, programmable I/O and all these resources interconnected by a switching fabric, allowing any resource to communicate with any other resource. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies.

With the described methodology and algorithms, a network refinement tool can be developed, which is integrated in the NoC design environment . The tool can be applied to four examples: a JPEG decoder (JPEG), a GSM Vocoder, a mobile phone baseband platform (Baseband) and a MP3 Decoder (MP3). The Baseband example is composed of JPEG decoder and GSM Vocoder running in parallel.

Download Network on Chip report

Mirror: http://snipurl.com/nochip Contributed by Keval

Deep Sub Micron (Seminar)

2007-08-21T06:19:00.000-07:00

Designing integrated circuits (ICs) using 0.18-micron and smaller process technologies poses tremendous challenges for IC design teams. The number of silicon failures that are caused by signal integrity problems is on the rise due to the lack of existing design tools and methodologies that can address these issues effectively. As a result, the importance of integrating signal integrity solutions into the IC design flow is growing.

The cost of such a failure is very high, and includes photomask costs, engineering costs, and opportunity cost due to delayed product introduction. Therefore electronic design automation tools have been developed to analyze, prevent, and correct these problems.

In most conventional IC design flows signal integrity analysis is performed as a post-layout activity. Unfortunately, this is the wrong time to be analyzing for signal integrity effects. Attempting to analyze and correct for these issues post-layout often results in costly and time consuming design iterations, failed schedules, reduced product performance and often, larger die sizes and poorer manufacturing yield

The timing in deep-submicron designs (designs using process technologies at 0.18 micron or lower), is inherently dominated by interconnect-dependent RC delay, not cell delay as used to be the case. Special tool capabilities are needed to ensure that the integrity of signals in the wires, and the integrity of the wires and other circuit components themselves are maintained. In general, signal integrity refers to the physical effects that cause signal deteriorations and physical deformations, both of which pose the threat of design failure. In the following pages we will discuss signal integrity issues including crosstalk noise, electromigration, IR drop, and special manufacturing rules.

Download Report and ppt

Mirror http://snipurl.com/deepsm Contributed By Abhishek

The beginning, of seminar topics

2007-08-21T02:45:00.000-07:00

Welcome to Seminars and Projects

Friends lets, celebrate the launching of this new blog, Seminars and Projects. In this Blog we will try to help, Juniors from various engineering branch to select a proper Seminar Topic. And if it is success we will provides Projects also..........

So lets spread the light of knowledge,

I am really thankful to my friends from CKPCET, Surat. who gave me their reports for purpose of sharing. I also thank them again for their encouragement and support.